1. Field of the Invention
The present invention relates to a semiconductor memory device suitable for storing in relatively small storage capacity and utilized for a battery-operated portable terminal and the like. More specifically, the present invention relates to a semiconductor memory device utilized for Static Random Access Memory (hereafter, referred to as SRAM) and the like realizing the operation in low power supply voltage and low power consumption.
2. Description of the Related Art
Conventionally, the technology in this field is, for example, described in the following documents:
Shingaku Gihou;
ICD97-52 (1997-6);
Institution of Electronics, Information and Communication Engineers;
Shibata and Morimura: a 1 V-operated 0.25 xcexcm SRAM macro cell for portable device (pages 1-8)
Recently, the SRAM is widely utilized as a cache memory in such as a large-scale integration (hereafter, referred to as LSI) for a specific use utilized for a mobile terminal and the like. The SRAM utilized as described above needs to be small in size and low in power consumption since the battery limited in voltage (for example, 1.2 V) is used as the power supply. As the power consumption becomes in proportion to the square of the power supply voltage, it is the most effective to lower the power supply voltage for saving the power consumption. However, when the power supply voltage is lowered, the operation speed of an MOS transistor used as one of a field-effect transistor (hereafter, referred to as FET), for example, configuring the SRAM becomes slow. If the threshold voltage of the MOS transistor is lowered in order to making the speed high, the amount of leak current caused by a sub-threshold voltage in standby is increased and the amount of the power consumption also increases at the same time.
To solve this problem, there is presented Multi-Threshold Complementary MOS transistor (hereafter, referred to as MTCMOS) as CMOS-LSI technology capable of being operated in low power consumption (for example, around 1 V) in an active state and low in power consumption caused by the leak current in standby. An example of SRAM configuration in the MTCMOS technology is to be shown as FIG. 11.
FIG. 11 is a schematic diagram showing an example of SRAM configuration in the conventional MTCMOS technology described in the documents presented above. In this SRAM configuration, a memory cell array 10 is configured by an MOS transistor with high threshold voltage and a peripheral circuit by an MOS transistor with low threshold voltage.
The memory cell array 10 has a plurality of word lines WL and a plurality of bit line pairs comprising a positive bit line BL and a negative bit line pair BL/, to the cross points of which a memory cell 11 for storing data is connected.
The peripheral circuit 20 has a row address decoder 21 connected to a plurality of word lines WL and an input/output circuit 22 connected to a plurality of bit line pairs of BL and BL/. The row address decoder 21 is a circuit decoding an address AD with a plurality of bits transmitted from the outside and a circuit selecting the word lines WL. The input/output circuit 22 has a column address decoder outputting a column select signal Y, that is, a bit line selection signal by decoding an address AD with a plurality of bits transmitted from the outside, turns a readout mode by read enable signal RE as a readout control signal, turns a write mode by write enable signal WE as a write control signal, and reads out or writes data DA with a plurality of bits in the memory cell 11 connected to the bit line pair of BL and BL/ selected by the column select signal Y.
Also in this SRAM configuration, in writing the data DA in a certain memory cell 11, for example, a word line WL connected to the memory cell 11 is selected by the row address decoder 21 while the bit line pair of BL and BL/ is selected at the input/output circuit 22, and the data DA transmitted from the outside is written in the memory cell 11.
In reading out the data in a certain memory cell 11, for example, a word line WL connected to the memory cell 11 is selected by the row address decoder 21 while the bit line pair of BL and BL/ is selected at the input/output circuit 22, and the data DA is read out from the memory cell 11 and output from the input/output circuit 22.
The peripheral circuit 20 is connected to the node of power supply voltage VDD (the voltage is, for example, around 1V) through a switch 23 of the MOS transistor with high threshold voltage. The switch 23 is controlled in turned-off state in standby by using a sleep signal xcfx86S to control the drain of battery (for example, 1.2 V) caused by sub-threshold leak current. It is difficult to adopt the MOS transistor with low threshold voltage to a plurality of memory cells 11 since the power supply cannot be cut off even in standby for maintaining the contents of memory. Further, it becomes necessary to consider the power consumption of a memory cell part in being operated by sub-threshold leak current if the scale of the memory cell array 10 becomes large.
This power consumption problem can be solved by configuring the memory cell part by CMOS and setting the threshold voltage at the MOS transistor high. However, since the power supply voltage VDD becomes lowered and bit line delay increases extremely in reading out, high operation speed cannot be obtained at an operation guarantee voltage (1 V, for example). In view of the operation speed, it is necessary to reduce the threshold voltage of the MOS transistor also in the memory cell.
In order to deal with this problem, the increase of power consumption caused by the sub-threshold leak current can be controlled while keeping the operation speed high by, for example, configuring the memory cell part by two kinds of MOS transistors different from each other in the threshold voltage and by using each MOS transistor properly in each circuit. An example of memory cell part configuration is to be shown as FIG. 12.
FIG. 12 is a circuit diagram showing an example of the configuration near the memory cell in the conventional MTCMOS technology described in the documents presented above. A memory cell 30 corresponds to the memory cell in FIG. 11 and has a flip-flop comprising two inverters 31 and 32 with high threshold voltage holding data in first and second nodes N1 and N2. An N-channel type MOS transistor (hereafter, referred to as NMOS) 33 for writing with high threshold voltage driven by a potential on the word line WL is connected between the positive bit line BL and the node Ni. An NMOS 34 for writing with high threshold voltage driven by a potential on the word line WL is connected between the negative bit line BL/ and the node N2.
A readout-acceleration circuit 35 is connected between the bit lines BL and BL/. The readout-acceleration circuit 35 accelerates the speed of readout operation by promoting the discharge of bit line capacitance and is configured by NMOS 35a and 35b for reading out with low threshold voltage connected to the bit lines BL and BL/ and by NMOS 35c and 35d with low threshold voltage driven by a potential at the nodes N1 and N2.
In order not to make the operation speed high but to make the power of the memory cell array 10 low, a virtual ground line VGND is arranged almost in parallel to the bit line BL. The one end of the virtual ground line VGND is connected to the node of ground potential GND through an NMOS 41 with high threshold voltage. The NMOS 41 is driven by two-input NOR circuit 42 with low threshold voltage. Since it is a waste of power to accelerate the writing cycle and the operation speed of non-selected bit line by using the acceleration circuit 35, the NMOS 41 is turned off and controlled in a floating state when the acceleration operation is not needed by using the NOR circuit 42 to input the read enable signal RE and the column select signal Y. As a result, the wasteful increase of power is controlled.
Next, the operation of memory cell 30 in FIG. 12 is to be explained. In writing, for example, when the word line WL turns xe2x80x9cHxe2x80x9d level and the NMOS 33 and 34 turn on, the data in the bit line pair of BL and BL/ is held in the nodes N1 and N2. Also in writing, the read enable signal RE turns xe2x80x9cHxe2x80x9d level, the output level of the NOR circuit 42 turns xe2x80x9cLxe2x80x9d and the NMOS 41 turns off. Consequently, the writing operation is not damaged.
In reading, the read enable signal RE and the column select signal Y turn xe2x80x9cLxe2x80x9d level, the voltage level of NOR circuit 42 turns xe2x80x9cHxe2x80x9d, and the NMOS 41 turns on. Then the virtual ground line VGND turns from floating state into ground potential GND. And then the word line turns xe2x80x9cHxe2x80x9d level and the NMOS 33, 34, 35a and 35b turn on. At this time, since either node N1 or N2 turns xe2x80x9cHxe2x80x9d level, either NMOS 35c or 35d turns on.
In reading xe2x80x9cHxe2x80x9d level at the node N1 and xe2x80x9cLxe2x80x9d level at the node N2, the NMOS 35d turns on and the NMOS 35c turns off. Hereby readout operation can be accelerated since the bit line is driven by an inverter 31 or 32 and the bit lines BL and BL/ are driven by the NMOS 35axcx9c35d with high capability of driving current and with low threshold voltage. In other words, since the NMOS 35d turns on in reading xe2x80x9cHxe2x80x9d level at the node N1 and xe2x80x9cLxe2x80x9d level at the node N2, the potential on the bit line BL/ is pulled down to the ground potential GND through the NMOS 35b, 35d and 41, to accelerate the readout operation.
Also, since the NMOS 41 with high threshold voltage becomes turned off by the output from the NOR circuit 42 in standby and the leak current caused by the sub-threshold current in the NMOS 35axcx9c35d with low threshold voltage, the power consumption can be saved.
By using the conventional memory cell 30 as shown in FIG. 12, however, the following problem still remains.
The readout operation is accelerated since, in reading, the NMOS 41 turns on, the virtual ground line VGND becomes connected to the node of ground potential GND, and the electric charge from the acceleration circuit 35 is discharged to the ground potential GND through the NMOS 41.
In writing operation performed after this readout operation, the NMOS 41 turns off and the virtual ground line VGND, the potential of which is near the ground potential GND, turns into floating state. For example, in writing inversion data with the node N1 xe2x80x9cHxe2x80x9d level and the node N2 xe2x80x9cLxe2x80x9d level (in other words, in writing xe2x80x9cLxe2x80x9d level on the node N1 and xe2x80x9cHxe2x80x9d level on the node N2), when the word line WL turns xe2x80x9cHxe2x80x9d level the NMOS 35a and 35b with low threshold voltage turn on before the NMOS 33 and 34 with high threshold voltage turn on. Then the NMOS 33 and 34 turn on after a while.
If the NMOS 35a and 35b turn on ahead, the NMOS 35d turns on since the node N1 turns xe2x80x9cHxe2x80x9d level with the NMOS 33 turned off. Consequently, the potential on the bit line BL/ is pulled down to the virtual ground line VGND in floating state near the ground potential GND through the NMOS 35b and 35d. As a result, the NMOS 33 and 34 turn on, it becomes hard to write the xe2x80x9cHxe2x80x9d level of the bit line BL/ on the node N2, and the speed of writing the inversion data is to be lowered.
In the first aspect of the present invention to achieve the above object, there is provided a semiconductor memory device comprising: a word line; a bit line pair having first and second bit lines and selected by a bit line selection signal; a power supply line; and a memory cell. The memory cell comprises: a data holding circuit holding data in first and second nodes; a first transistor with high threshold voltage connected between the first bit line and the first node and driven by a potential on the word line; a second transistor with high threshold voltage connected between the second bit line and the second node and driven by a potential on the word line; a third transistor with low threshold voltage connected between the first bit line and a third node; a fourth transistor with low threshold voltage connected between the second bit line and a fourth node; a fifth transistor with low threshold voltage connected between the third node and the power supply line and driven by data in the second node; and a sixth transistor with low threshold voltage connected between the fourth node and the power supply line and driven by data in the first node.
Further in the first aspect of the present invention, the memory cell comprises: a seventh transistor with high threshold voltage connected between the power supply line and a fifth node with a specific potential and becoming turned-on in writing and turned-off in reading out; and a logical circuit. The logical circuit makes the third and fourth transistors turned-off in writing and the third and fourth transistors turned-on in reading out, based on the potential on the word line and readout control signal or based on the potential on the word line, the readout control signal and the bit line selection signal.
By adopting this configuration, the seventh transistor turns off and the power supply line turns into floating state, while the third and the fourth transistors turn off by the logical circuit in writing. Hereby the operation speed is not lowered in writing the inversion data. Also, the seventh transistor turns on and the third and fourth transistors turn on by the logical circuit in reading, while the readout operation is accelerated by the thirdxcx9csixth transistors.